RK3288 查看ddr频率

2018/03/06 17:14
阅读数 14

转载请注明出处:https://www.cnblogs.com/lialong1st/p/8515135.html

 

CPU:RK3288

系统:Android 5.1

 

RK3288 查看 ddr 当前频率的方式有两种,第一种是通过 adb 查看,第二种是在串口打印中通过指令查看

1、通过 adb 查看

$ adb shell
root@rk3288:/ # cd sys/kernel/debug/clk
cd sys/kernel/debug/clk
root@rk3288:/sys/kernel/debug/clk # cat clk_summary |grep ddr
cat clk_summary |grep ddr
       clk_ddr                  0           0            396000000

 

2、在串口打印中通过指令查看当前ddr频率可以,但是adb中是看不到的。

shell@firefly:/ $ cd sys/dvfs
shell@firefly:/sys/dvfs $ ls
cpu_temp_enable
cpu_temp_target
dvfs_tree
shell@firefly:/sys/dvfs $ cat dvfs_tree
/system/bin/sh: cat: dvfs_tree: Permission denied     // 没有权限
1|shell@firefly:/sys/dvfs $ su     // 获取root权限
shell@firefly:/sys/dvfs # cat dvfs_tree
[ 107.795152] -------------DVFS TREE-----------
[ 107.795152] 
[ 107.795152] 
[ 107.795205] DVFS TREE:
[ 107.795220] |
[ 107.795220] |- voltage domain:vd_gpu
[ 107.795239] |- current voltage:900000
[ 107.795252] |- current regu_mode:UNKNOWN
[ 107.795269] | |
[ 107.795269] | |- power domain:pd_gpu, status = OFF, current volt = 900000, current regu_mode = UNKNOWN
[ 107.795295] | | |
[ 107.795295] | | |- clock: clk_gpu current: rate 198000, volt = 900000, enable_dvfs = ENABLE
[ 107.795321] | | |- clk limit(enable):[198000000, 480000000]; last set rate = 198000
[ 107.795336] | | | |- freq = 198000, volt = 900000
[ 107.795350] | | | |- freq = 297000, volt = 950000
[ 107.795363] | | | |- freq = 417000, volt = 1100000
[ 107.795377] | | | |- freq = 480000, volt = 1150000
[ 107.795392] | | |- clock: clk_gpu current: rate 198000, regu_mode = UNKNOWN, regu_mode_en = 0
[ 107.795407] |
[ 107.795407] |- voltage domain:vd_logic
[ 107.795425] |- current voltage:1125000
[ 107.795437] |- current regu_mode:UNKNOWN
[ 107.795452] | |
[ 107.795452] | |- power domain:pd_vio, status = OFF, current volt = 0, current regu_mode = UNKNOWN
[ 107.795476] | | |
[ 107.795476] | | |- clock: aclk_vio1 current: rate 594000, volt = 0, enable_dvfs = ENABLE
[ 107.795501] | | |- clk limit(enable):[99000000, 297000000]; last set rate = 594000
[ 107.795516] | | | |- freq = 99000, volt = 1100000
[ 107.795530] | | | |- freq = 297000, volt = 1100000
[ 107.795545] | | |- clock: aclk_vio1 current: rate 594000, regu_mode = UNKNOWN, regu_mode_en = 0
[ 107.795563] | |
[ 107.795563] | |- power domain:pd_ddr, status = OFF, current volt = 1125000, current regu_mode = UNKNOWN
[ 107.795587] | | |
[ 107.795587] | | |- clock: clk_ddr current: rate 456000, volt = 1125000, enable_dvfs = ENABLE     // 456000为ddr频率,单位为KHz
[ 107.795612] | | |- clk limit(enable):[200000000, 528000000]; last set rate = 456000
[ 107.795626] | | | |- freq = 200000, volt = 1075000
[ 107.795640] | | | |- freq = 300000, volt = 1075000
[ 107.795653] | | | |- freq = 456000, volt = 1125000
[ 107.795666] | | | |- freq = 528000, volt = 1150000
[ 107.795682] | | |- clock: clk_ddr current: rate 456000, regu_mode = UNKNOWN, regu_mode_en = 0
[ 107.795696] |
[ 107.795696] |- voltage domain:vd_arm
[ 107.795714] |- current voltage:950000
[ 107.795726] |- current regu_mode:UNKNOWN
[ 107.795740] | |
[ 107.795740] | |- power domain:pd_core, status = OFF, current volt = 950000, current regu_mode = UNKNOWN
[ 107.795765] | | |
[ 107.795765] | | |- clock: clk_core current: rate 600000, volt = 950000, enable_dvfs = ENABLE
[ 107.795789] | | |- clk limit(enable):[126000000, 1800000000]; last set rate = 600000
[ 107.795804] | | | |- freq = 126000, volt = 900000
[ 107.795817] | | | |- freq = 216000, volt = 900000
[ 107.795830] | | | |- freq = 312000, volt = 900000
[ 107.795843] | | | |- freq = 408000, volt = 900000
[ 107.795856] | | | |- freq = 600000, volt = 950000
[ 107.795869] | | | |- freq = 696000, volt = 950000
[ 107.795882] | | | |- freq = 816000, volt = 1000000
[ 107.795895] | | | |- freq = 1008000, volt = 1050000
[ 107.795909] | | | |- freq = 1200000, volt = 1100000
[ 107.795922] | | | |- freq = 1416000, volt = 1200000
[ 107.795936] | | | |- freq = 1512000, volt = 1300000
[ 107.795949] | | | |- freq = 1608000, volt = 1350000
[ 107.795962] | | | |- freq = 1704000, volt = 1350000
[ 107.795975] | | | |- freq = 1800000, volt = 1350000
[ 107.795990] | | |- clock: clk_core current: rate 600000, regu_mode = UNKNOWN, regu_mode_en = 0
[ 107.796004] -------------DVFS TREE END------------

 

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