Design of Cost Efficient Interconnect Processing Unit

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2019/04/12 00:00
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A network-on-chip or NoC has become a key component in most complex digital chips. As the number of components per chip continues to double every two years all but the smallest chips today are multicore or manycore chips; that is, they consist of a number of separate cores, processors or fixed-function accelerators, along with memory arrays and input/output units. Mainstream general purpose processors are currently available as chip multiprocessors (CMPs) with four cores and tens of cores are expected by the end of the decade. Embedded systems-on-a-chip (SoCs) already have 10s of cores and will have 100s of cores within a decade. Historically buses or crosspoint switches were used to connect multiple cores on a chip. Above four cores, however, the limited bandwidth of a bus becomes a major limitation, and above 8 or 16 cores, crosspoint switches become prohibitively expensive and unwieldy. Only a NoC provides the scalability needed for emerging multicore chips

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